1. Technical Field of the Invention
This invention relates generally to radio receivers and more particularly to filtering within radio receivers.
2. Description of Related Art
The drive towards systems-on-chip solutions for wireless radio applications continues to replace traditionally analog signal processing tasks with digital processing to exploit the continued shrinkage in die area and reduction in power consumption of digital CMOS technology. The idea is to relax analog signal processing requirements and relegate more processing to the digital domain where, in addition to the reduced silicon area requirements, the processing is insensitive to process and temperature variations.
Since an increasing amount of the signal processing of the modern radio is relegated to the digital domain, many efforts have gone into developing hardware efficient, low power digital signal processing algorithms that perform the processing necessary in the receiver sections of the radio. Probably the most important task in the digital signal processing of radios is the task of filtering. Filtering is used to remove undesired noise and interfering signals in order to provide high signal-to-noise ratio (SNR) in the processing path.
Sharp digital low pass filters (LPFs) with carefully selected bandwidths are commonly employed in radio receivers to remove interferers and noise. Such digital LPFs are often referred to as “channel-select” filters. These filters must be designed to be very frequency selective while maintaining linear phase response in order not to cause distortion of the received signal. Employing digital filters with non-linear phase response is possible, but undesirable, since this would generally require compensation in later processing stages. Such compensation typically requires a substantial amount of digital processing.
A popular class of filters for channel-select filtering is finite impulse response (FIR) filters because of their inherent linear phase response. As the name implies, an FIR filter, H(z), can be represented in the discrete-time domain with a finite sequence of coefficients as in the following general form of the Z-transform of the impulse response
                                          H            ⁡                          (              z              )                                =                                                    h                0                            +                                                h                  1                                ⁢                                  z                                      -                    1                                                              +              …              ⁢                                                          +                                                h                  N                                ⁢                                  z                                      -                    N                                                                        =                                          ∑                                  i                  =                  0                                N                            ⁢                                                          ⁢                                                h                  i                                ⁢                                  z                                      -                    i                                                                                      ,                            (        1        )            FIR filters are commonly followed by a down-sampling module that reduces the sampling rate of the digital signal. The combined FIR filter and down-sampler is referred to as a channel-select decimation filter. Decimation filters are often encountered in receivers since the analog-to-digital converters (ADCs) are typically high sampling rate devices. As a result, it is often desired to reduce the sampling rate as part of the filtering process, which reduces power consumption and complexity of the subsequent processing stages.
In addition to performing frequency selective filtering and reducing the sampling rate, decimation filters are typically also used to introduce magnitude equalization in the signal path of the receiver. Magnitude equalization is the task of compensating for the in-band magnitude droop caused by the preceding analog filtering stages. Typically, analog filtering imposes some degree of in-band droop in the signal path in order to provide adequate attenuation of close-in interferers. This in-band droop represents signal distortion, and may lead to degraded receiver performance. Thus, for optimal receiver performance, this magnitude distortion must be compensated for in the digital domain by some equalization mechanism. The result is that the combined magnitude response of the analog and digital filtering as closely as possible resembles that of an ideal “brick-wall” filter.
A disadvantage of decimation filters is that they typically require a large number of multiplications and additions to perform the narrowband frequency selective low pass filtering and magnitude equalization needed in high-performance receivers. Defined as the standard measure of hardware complexity of decimation filters, the number of multiplications and additions needed per clock cycle is directly related to power consumption and required chip die area. Thus, for low power and low cost radios, it is imperative to reduce the hardware complexity of the digital filters as much as possible.
Therefore, hardware efficient decimation filters have recently been introduced that perform channel magnitude equalization, are low-power, and are capable of performing narrowband frequency selective low pass and equalization filtering without the use of a large number of multipliers. These hardware efficient decimation filters typically incorporate multiple low pass filter stages that utilize simple adders to produce channel-selected signals. However, the reduced hardware complexity also necessitates that the design of these decimation filters be specifically tailored to a particular bandwidth. In situations where the signal is too weak to effectively remove undesired noise and interfering signals, it may be desirable to increase the bandwidth to improve the signal power.
Therefore, a need exists for a hardware efficient decimation filter that is capable of performing narrowband frequency selective low pass and equalization filtering with a programmable bandwidth.